A frequency synthesizer is a circuit that generates one or more output signals whose frequency bears a prescribed relation to the frequency of an input reference signal. Such circuits are used as accurate frequency sources in a wide variety of electronic apparatus.
Generally a frequency synthesizer provides an output frequency ##EQU1## where .function..sub.i is the input or reference frequency and where the values of N and M are integers chosen to provide the desired ratio between the input and output frequencies.
A common form of frequency synthesizer uses a phase-locked loop (PLL) to set the output frequency. In FIG. 1 there is shown the basic circuit 10 of a common form of prior art PLL frequency synthesizer. A signal of frequency .function..sub.i is supplied as an input to a divider circuit 12. The output of the divider circuit is supplied as an input to the PLL 14, an element of which is a divider circuit. For purposes of illustration, the divider circuit has been shown as a separate element 16 in the feedback loop of the PLL, although more precisely it can be viewed to be a part of the PLL. An expanded view of a PLL is shown in FIG. 3. As shown in FIG. 1, the divider 12 divides by the integer M and the divider 16 by the integer N. The signal of output frequency .function..sub.o from the PLL has a frequency of .function..sub.i N/M.
The principles of PLL frequency synthesizers are set forth in a book entitled Phase-Locked Loop Circuit Design by D. H. Wolaver, Prentice-Hall, Englewood Cliffs, N.J., (1991) with particular reference to Chapter 11, pages 239-260, "Frequency Synthesizers" and the teachings of the book are incorporated herein by reference.
A PLL generally comprises a closed loop that includes a phase detector (PD) and a voltage controlled oscillator (VCO), along with a frequency divider that divides by N. When in lock, the frequency .function..sub.i /M and the frequency .function..sub.o /N that serve as frequencies of the two inputs to the phase detector are equal, so that the output frequency .function..sub.o is equal to .function..sub.i N/M. A common form of VCO for use in a PLL is a ring oscillator that employs a series of delay elements to provide the desired frequency range of operation.
The bandwidth of the closed loop is known to be an important factor in controlling the jitter in the output frequency of a PLL frequency synthesizer. In particular, a wide loop bandwidth can offer a higher suppression of the VCO phase noise than a narrow loop bandwidth. Quantitatively the output jitter is inversely proportional to the square root of the loop bandwidth. However loop stability considerations limit the closed loop bandwidth that can be safely used. The limit is about a tenth of the rate at which the PD in the PLL is updating. Thus large M and/or N values in the PLL shown in FIG. 1 restrict the feasible bandwidth of the loop.
The present invention seeks to avoid this problem and makes it feasible to employ relatively large values of M and/or N defining the relation between the input and output frequencies without violating loop stability considerations.